Processor [Intel(R) Core(TM) i7-4650U CPU @ 1.70GHz] |- Architecture [Haswell/Ultra Low TDP] |- Vendor ID [GenuineIntel] |- Microcode [0x00000016] |- Signature [ 06_45] |- Stepping [ 1] |- Online CPU [ 4/ 4] |- Base Clock [ 99.768] |- Frequency (MHz) Ratio Min 798.15 < 8 > Max 2294.67 < 23 > |- Factory [100.000] 1700 [ 17 ] |- Performance |- P-State TGT 798.15 < 8 > |- Turbo Boost [ UNLOCK] 1C 3292.36 < 33 > 2C 2893.28 < 29 > 3C 2893.28 < 29 > 4C 2893.28 < 29 > |- Uncore [ LOCK] Min 798.15 [ 8 ] Max 2294.67 [ 23 ] |- TDP Level < 0:3 > |- Programmable [ UNLOCK] |- Configuration [ UNLOCK] |- Turbo Activation [ UNLOCK] Nominal 1696.06 [ 17 ] Level1 798.15 [ 8 ] Level2 2294.67 [ 23 ] Turbo 1596.29 < 16 > Instruction Set Extensions |- 3DNow!/Ext [N/N] ADX [N] AES [Y] AVX/AVX2 [Y/Y] |- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N] |- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N] |- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNMI [N] AVX512-ALG [N] |- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] |- AVX512-BF16 [N] BMI1/BMI2 [Y/Y] CLWB [N] CLFLUSH/O [Y/N] |- CLAC-STAC [N] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y] |- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y] |- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y] |- POPCNT [Y] RDRAND [Y] RDSEED [N] RDTSCP [Y] |- SEP [Y] SHA [N] SSE [Y] SSE2 [Y] |- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y] |- SERIALIZE [N] SYSCALL [Y] SGX [N] RDPID [N] Features |- 1 GB Pages Support 1GB-PAGES [Capable] |- Advanced Configuration & Power Interface ACPI [Capable] |- Advanced Programmable Interrupt Controller APIC [Capable] |- Core Multi-Processing CMP Legacy [Missing] |- L1 Data Cache Context ID CNXT-ID [Missing] |- Direct Cache Access DCA [Missing] |- Debugging Extension DE [Capable] |- Debug Store & Precise Event Based Sampling DS, PEBS [Capable] |- CPL Qualified Debug Store DS-CPL [Capable] |- 64-Bit Debug Store DTES64 [Capable] |- Fast-String Operation Fast-Strings [Capable] |- Fused Multiply Add FMA | FMA4 [Capable] |- Hardware Lock Elision HLE [Capable] |- Instruction Based Sampling IBS [Missing] |- Long Mode 64 bits IA64 | LM [Capable] |- LightWeight Profiling LWP [Missing] |- Machine-Check Architecture MCA [Capable] |- Memory Protection Extensions MPX [Missing] |- Model Specific Registers MSR [Capable] |- Memory Type Range Registers MTRR [Capable] |- OS-Enabled Ext. State Management OSXSAVE [Capable] |- Physical Address Extension PAE [Capable] |- Page Attribute Table PAT [Capable] |- Pending Break Enable PBE [Capable] |- Process Context Identifiers PCID [Capable] |- Perfmon and Debug Capability PDCM [Capable] |- Page Global Enable PGE [Capable] |- Page Size Extension PSE [Capable] |- 36-bit Page Size Extension PSE36 [Capable] |- Processor Serial Number PSN [Missing] |- Resource Director Technology/PQE RDT-A [Missing] |- Resource Director Technology/PQM RDT-M [Missing] |- Restricted Transactional Memory RTM [Capable] |- Safer Mode Extensions SMX [Capable] |- Self-Snoop SS [Capable] |- Supervisor-Mode Access Prevention SMAP [Missing] |- Supervisor-Mode Execution Prevention SMEP [Capable] |- Time Stamp Counter TSC [Invariant] |- Time Stamp Counter Deadline TSC-DEADLINE [Capable] |- TSX Force Abort MSR Register TSX-ABORT [Missing] |- TSX Suspend Load Address Tracking TSX-LDTRK [Missing] |- User-Mode Instruction Prevention UMIP [Missing] |- Virtual Mode Extension VME [Capable] |- Virtual Machine Extensions VMX [Capable] |- Extended xAPIC Support x2APIC [ x2APIC] |- Execution Disable Bit Support XD-Bit [Capable] |- XSAVE/XSTOR States XSAVE [Capable] |- xTPR Update Control xTPR [Capable] Mitigation mechanisms |- Indirect Branch Restricted Speculation IBRS [Missing] |- Indirect Branch Prediction Barrier IBPB [Missing] |- Single Thread Indirect Branch Predictor STIBP [Missing] |- Speculative Store Bypass Disable SSBD [Missing] |- Writeback & invalidate the L1 data cache L1D-FLUSH [Missing] |- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [Missing] |- Architectural - Buffer Overwriting MD-CLEAR [Missing] |- Architectural - Rogue Data Cache Load RDCL_NO [Missing] |- Architectural - Enhanced IBRS IBRS_ALL [Missing] |- Architectural - Return Stack Buffer Alternate RSBA [Missing] |- Architectural - Speculative Store Bypass SSB_NO [Missing] |- Architectural - Microarchitectural Data Sampling MDS_NO [Missing] |- Architectural - TSX Asynchronous Abort TAA_NO [Missing] |- Architectural - Page Size Change MCE PSCHANGE_MC_NO [Missing] |- Architectural - STLB QoS STLB [Missing] |- Architectural - Functional Safety Island FuSa [Missing] |- Architectural - RSM in CPL0 only RSM [Missing] |- Architectural - Split Locked Access Exception SPLA [Missing] |- Architectural - Snoop Filter QoS Mask SNOOP_FILTER [Missing] Technologies |- Data Cache Unit |- L1 Prefetcher L1 HW < ON> |- L1 IP Prefetcher L1 HW IP < ON> |- L2 Prefetcher L2 HW < ON> |- L2 Line Prefetcher L2 HW CL < ON> |- System Management Mode SMM-Dual [OFF] |- Hyper-Threading HTT [ ON] |- SpeedStep EIST < ON> |- Dynamic Acceleration IDA [ ON] |- Turbo Boost TURBO < ON> |- Energy Efficiency Optimization EEO |- Race To Halt Optimization R2H |- Watchdog Timer TCO < ON> |- Virtualization VMX [OFF] |- I/O MMU VT-d [ ON] |- Version [ N/A] |- Hypervisor [OFF] |- Vendor ID [ N/A] Performance Monitoring |- Version PM [ 3] |- Counters: General Fixed | 4 x 48 bits 3 x 48 bits |- Enhanced Halt State C1E |- C1 Auto Demotion C1A < ON> |- C3 Auto Demotion C3A < ON> |- C1 UnDemotion C1U < ON> |- C3 UnDemotion C3U < ON> |- C6 Core Demotion CC6 |- C6 Module Demotion MC6 |- Legacy Frequency ID control FID [OFF] |- Legacy Voltage ID control VID [OFF] |- P-State Hardware Coordination Feedback MPERF/APERF [ ON] |- Hardware-Controlled Performance States HWP [OFF] |- Hardware Duty Cycling HDC [OFF] |- Package C-States |- Configuration Control CONFIG [ LOCK] |- Lowest C-State LIMIT < C10> |- I/O MWAIT Redirection IOMWAIT < Enable> |- Max C-State Inclusion RANGE < UNS> |- Core C-States |- C-States Base Address BAR [ 0x1814] |- MONITOR/MWAIT |- State index: #0 #1 #2 #3 #4 #5 #6 #7 |- Sub C-State: 0 2 1 2 4 1 1 1 |- Core Cycles [Capable] |- Instructions Retired [Capable] |- Reference Cycles [Capable] |- Last Level Cache References [Capable] |- Last Level Cache Misses [Capable] |- Branch Instructions Retired [Capable] |- Branch Mispredicts Retired [Capable] |- Top-down slots Counter [Capable] Power, Current & Thermal |- Clock Modulation ODCM |- DutyCycle [ 0.00%] |- Power Management PWR MGMT [ LOCK] |- Energy Policy Bias Hint < 6> |- Energy Policy HWP EPP [ 0] |- Junction Temperature TjMax [ 0:100C] |- Digital Thermal Sensor DTS [Capable] |- Power Limit Notification PLN [Capable] |- Package Thermal Management PTM [Capable] |- Thermal Monitor 1 TM1 [Capable] |- Thermal Monitor 2 TM2 [Capable] |- Thermal Design Power TDP [ 15 W] |- Minimum Power Min [Missing] |- Maximum Power Max [Missing] |- Thermal Design Power Package < Enable> |- Power Limit (28 sec) PL1 < 25 W> |- Power Limit (1 sec) PL2 < 25 W> |- Thermal Design Power Core |- Power Limit PL1 [Missing] |- Thermal Design Power Uncore |- Power Limit PL1 [Missing] |- Thermal Design Power DRAM |- Power Limit PL1 [Missing] |- Thermal Design Power Platform |- Power Limit PL1 [Missing] |- Power Limit PL2 [Missing] |- Electrical Design Current EDC [Missing] |- Thermal Design Current TDC [Missing] |- Units |- Power watt [ 0.125000000] |- Energy joule [ 0.000061035] |- Window second [ 0.000976562]